The continuing evolution of complex data/signal analysis/processing requirements in industrial, scientific and military environments has been accompanied by a demand for an increase in data/signal processing capacity, speed and integration density of microelectronic implementations of the processing hardware. To handle the enormous variety of processing algorithms, the programmable microprocessor has been typically employed as the principal signal processing mechanism. While the microprocessor approach, because of programmability and memory expansion capability, offers flexibility in its application to essentially any degree of signal processing complexity, its architecture and operation impart speed constraints on its practical use in highly dynamic signal processing environments such as sophisticated avionics and weapons delivery systems of state of the art military aircraft.
One proposal for circumventing the performance limitations of conventional microprocessor architectures has been to use a custom signal processor configured to implement a specific signal processing algorithm. One such algorithm that has been found to be especially attractive in the dynamic signal processing environment is the Fast Fourier Transform (FFT). Computational execution of the FFT is typically accomplished through the use of a very large multiplier-adder matrix which, when mapped into a semiconductor architecture, requires a considerable wafer occupation area. Because signal processing applications of the type mentioned above are practically realizable only through the use of parallel processor architectures, the final processor configuration becomes both costly and cumbersome to implement.